1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to an organic electroluminescent display (OELD) device and a method of fabricating an OELD device.
2. Discussion of the Related Art
In the past, many display devices have employed cathode-ray tubes (CRTs) to display images. However, various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display (FED) devices, and electro-luminescent display (ELD) devices, are currently being developed as substitutes for the CRTs. Among these various types of flat panel displays, the PDP devices have advantages of large display size, but have disadvantages of heaviness and high power consumption. Similarly, the LCD devices have advantages of thin profile and low power consumption, but have disadvantages of small display size. However, the OELD devices are luminescent displays having advantages of fast response time, high brightness, and wide viewing angles.
FIG. 1 is a cross-sectional view of an OELD device according to the related art.
As illustrated in FIG. 1, an OELD device includes first and second substrates 10 and 60 facing each other and bonded together with a sealant 70. The first substrate 10 includes a thin film transistor T, an array layer AL and an organic emitting diode E including a first electrode 48 and an organic emitting layer 54 within a pixel region P, and a second electrode 56. The second substrate 60 has a recessed portion 62 filled with a desiccant 64 for blocking entry of outer moisture.
In FIG. 1, when the first electrode 48 is formed of a transparent material, light emitted from the organic emitting layer 54 is transmitted toward the first substrate 10. Thus, this OELD device is categorized as a bottom emission-type OELD device.
FIG. 2A is a plan view of a pixel region of an OELD device according to the related art, and FIG. 2B is a cross-sectional view, which shows a driving thin film transistor, taken along a line IIb-IIb of FIG. 2A.
As illustrated in FIG. 2A, in a pixel region P of a first substrate 10, a data line 42 and a gate line 22 crossing each other, a switching thin film transistor Ts, a driving thin film transistor Td, a power line 28 and an organic emitting diode E.
As illustrated in FIG. 2B, a buffer layer 12 is disposed on a first substrate 10. A semiconductor pattern 14 and a first capacitor electrode 16 is disposed on the buffer layer 12. A gate insulating layer 18 and a gate electrode 20 is disposed on the semiconductor pattern 14. The semiconductor pattern 14 includes an active region AR at a center portion, a drain region DR at a left portion and a source region at a right portion SR.
A first passivation layer 24 is disposed on the gate electrode 20. A power electrode 26 as a second capacitor electrode extended from the power line 28 is disposed on the first passivation layer 24 corresponding to the first capacitor electrode 16. The power electrode 26 as the second capacitor electrode and the first capacitor electrode 16 define a storage capacitor Cst.
A second passivation layer 30 is disposed on the power electrode 26. The first and second passivation layers 24 and 30 have first and second contact holes 32 and 34 exposing the source and drain regions SR and DR. Furthermore, the second passivation layer 30 have a third contact hole 36 exposing the power electrode 26.
Source and drain electrodes 38 and 40 are disposed on the second passivation layer 30. The source and drain electrodes 38 and 40 contact the source and drain regions SR and DR through the first and second contact hole 32 and 34, respectively. Furthermore, the source electrode 38 contacts the power electrode 26 through the third contact hole 36. A third passivation layer 44 is disposed on the source and drain electrodes 38 and 40 and has a fourth contact hole 46 exposing the drain electrode 40.
An organic emitting diode E including a first electrode 48, an organic emitting layer 54 and a second electrode 56 is disposed on the third passivation layer 44. The first electrode 48 is disposed on the third passivation layer 44 and contacts the drain electrode through the fourth contact hole 46. An inter layer 50 covers an end portion of the first electrode 48 and has an opening 51 exposing the first electrode 48. The organic emitting layer 54 covers the opening 51 and a portion of the inter layer 50. The second electrode 56 is disposed entirely on the substrate 10 having the organic emitting layer 54.
In the related art OELD device, because the switching and driving thin film transistors and the organic emitting diode are both formed on the first (lower) substrate, the production efficiency of the OELD device is reduced. For example, when one of the switching and driving thin film transistors and the organic emitting diode is determined to have a defect after fabrication, then the first (lower) substrate is considered unacceptable, and thus the production efficiency of the OELD device is reduced. Furthermore, when the OELD device is a bottom emission-type OELD device in which the first electrode of the organic emitting diode is formed of a transparent material, the aperture ratio of the OELD device is reduced and high resolution is difficult to achieve, because the switching and driving thin film transistors and metal lines block bottom emission of the light.